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200504t20202020xxk o 000 0 eng d
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▼a 9781785618864
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▼a 1785618865
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▼z 1785618857
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▼z 9781785618857
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▼a 2449704
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▼a (OCoLC)1153064237
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▼a TK7872.P38
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▼a 621.3815364
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▼a Phase-locked frequency generation and clocking:
▼b architectures and circuits for modern wireless and wireline systems /:
▼c edited by Woogeun Rhee. -
246
▼a Architectures and circuits for modern wireless and wireline systems
-
260
▼a London, UK:
▼b The Institution of Engineering and Technology,
▼c 2020. -
300
▼a 1 online resource (xvii, 715 pages):
▼b illustrations. -
336
▼a text
▼b txt
▼2 rdacontent -
337
▼a computer
▼b c
▼2 rdamedia -
338
▼a online resource
▼b cr
▼2 rdacarrier -
490
▼a IET materials, circuits and devices series;
▼v 64 -
504
▼a Includes bibliographical references and index (pages 697-715).
-
505
▼a Evolution of monolithic phase-locked loops / Woogeun Rhee -- Fractional-N frequency synthesis / Sudharkar Pamarti -- Clock data recovery : a system perspective / Fulvio Spagna -- Silicon-based THz frequency synthesizers with wide locking range / Payam Heydari -- Time-to-digital converters / Fa Foster Dai and Hechen Wang -- Bang bang digital PLLs for wireless systems / Salvatore Levantino and Carolo Samori -- Hybrid PLLs / Mark Ferriss and Daniel Friedman -- Spur mitigation techniques for DPLL architecture / Cheng-Ru Ho and Mike Shuo-Wei Chen -- Fully synthesized digital PLL / Bangan Liu, Wei Deng, and Kenichi Okada -- Ultra-low power ADPLL / Hanli Liu and Kenichi Okada -- Integrated LC oscillators / Jun Li and Yiwu Tang -- Mm-wave and sub-THz CMOS VCOs / Xiaolong Liu and Howard C. Luong -- Ultra-low phase noise ADPLL for millimeter wave / Zhirui Zong and Robert Bogdan Staszewski -- DTC-based subsampling PLLs for low-noise synthesis and two-point modulation / Nereo Markulic, Jan Craninckx and Piet Wambacq -- Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering / Ni Xu -- An overview of CDR in ultra-high-speed wireline transceivers / Jay Im and Hongtao Zhang -- Clock and data recovery for optical links / Wei Zen Chen, Ming-Chiuan Su, and Yuan-Sheng Lee -- Digital clock and data recovery circuits / Saurabh Saxena and Pavan Kumar Hanumolu -- Spread spectrum clock generator : a low-cost EMI solution / Minyoung Song and Chulwoo Kim -- High-performance CMOS clock distribution / Xunjun Mo, Nijwm Wary and Tony Chan Carusone -- Sub-sampling PLL techniques / Xiang Gao, Eric Klumperink and Bram Nauta -- PLLs with nested frequency-locked loop / Taekwang Jang, Dong-in Kim and SeongHwan Cho -- Time amplified charge pump PLL / Ping-Ying Wang -- Multiplying DLLs / Shiheng Yang, Jun Yin, Pui-In Mak and Rui P. Martins -- Widespread PLLs / Long Kong and Behzad Razavi.
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520
▼a The book has 25 chapters and is divided into 5 parts. The first part which is about Basic architectures and system perspectives deals with Evolution of monolithic phase-locked loops; Fractional-N frequency synthesis; Clock data recovery: a system perspective; and Silicon-based THz frequency synthesizers with wide locking range. The second part which is about Digital-intensive phase-locked loops covers Time-to-digital converters; Bang-bang digital PLLs for wireless systems; Hybrid PLLs; Spur mitigation techniques for DPLL architecture; Fully synthesized digital PLL; and Ultra-low-power ADPLL. The third part which is about Low-noise frequency generation and modulation covers Integrated LC oscillators; Mm-wave and sub-THz CMOS VCOs; Ultra-low phase noise ADPLL for millimeter wave; DTC-based subsampling PLLs for low-noise synthesis and two-point modulation; and Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering. The fourth part which is about Clock-and-data recovery and clocking covers An overview of CDR in ultra-high-speed wireline transceivers; Clock and data recovery for optical links; Digital clock and data recovery circuits; Spread spectrum clock generator: a low-cost EMI solution; and High-performance CMOS clock distribution. Finally, part five which is about Advanced clock/frequency generation deals with Sub-sampling PLL techniques; PLLs with nested frequency-locked loop; Time amplified charge pump PLL; Multiplying DLLs; and Wideband PLLs.
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588
▼a Online resource; title from PDF title page (IET Digital, viewed June 9, 2020).
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590
▼a Master record variable field(s) change: 050, 082
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650
▼a Phase-locked loops.
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650
▼a Phase-locked loops
▼2 fast
▼0 (OCoLC)fst01060416 -
650
▼a charge pump circuits.
▼2 inspect -
650
▼a clock and data recovery circuits.
▼2 inspect -
650
▼a clock distribution networks.
▼2 inspect -
650
▼a clocks.
▼2 inspect -
650
▼a CMOS digital integrated circuits.
▼2 inspect -
650
▼a digital phase locked loops.
▼2 inspect -
650
▼a direct digital synthesis.
▼2 inspect -
650
▼a electromagnetic interference.
▼2 inspect -
650
▼a elemental semiconductors.
▼2 inspect -
650
▼a field effect MIMIC.
▼2 inspect -
650
▼a field effect MMIC.
▼2 inspect -
650
▼a FIR filters.
▼2 inspect -
650
▼a frequency locked loops.
▼2 inspect -
650
▼a frequency modulation.
▼2 inspect -
650
▼a LC circuits.
▼2 inspect -
650
▼a low-power electronics.
▼2 inspect -
650
▼a millimetre wave oscillators.
▼2 inspect -
650
▼a MMIC oscillators.
▼2 inspect -
650
▼a multiplying circuits.
▼2 inspect -
650
▼a optical links.
▼2 inspect -
650
▼a phase locked oscillators.
▼2 inspect -
650
▼a phase noise.
▼2 inspect -
650
▼a silicon.
▼2 inspect -
650
▼a submillimetre wave integrated circuits.
▼2 inspect -
650
▼a submillimetre wave oscillators.
▼2 inspect -
650
▼a time-digital conversion.
▼2 inspect -
650
▼a transceivers.
▼2 inspect -
650
▼a voltage-controlled oscillators.
▼2 inspect -
655
▼a Electronic books.
-
700
▼a Rhee, Woogeun,
▼d 1968-,
▼e editor. -
776
▼i Print version:
▼t Phase-locked frequency generation and clocking.
▼d [S.l.] : INST OF ENGIN AND TECH, 2020,
▼z 1785618857
▼w (OCoLC)1122191813 -
830
▼a Materials, circuits and devices series;
▼v 64. -
856
▼3 EBSCOhost
▼u http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=2449704 -
938
▼a YBP Library Services
▼b YANK
▼n 301251697 -
938
▼a EBSCOhost
▼b EBSC
▼n 2449704 -
990
▼a 강리원
-
991
▼a eBook
-
994
▼a 92
▼b N$T
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LDR
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상세정보
Phase-locked frequency generation and clocking : architectures and circuits for modern wireless and wireline systems
QR코드| 자료유형 : | eBook |
|---|---|
| ISBN : | 9781785618864 |
| ISBN : | 1785618865 |
| ISBN : | |
| ISBN : | |
| 서명/저자사항 : | Phase-locked frequency generation and clocking: architectures and circuits for modern wireless and wireline systems /: edited by Woogeun Rhee. |
| 기타표제 : | Architectures and circuits for modern wireless and wireline systems |
| 발행사항 : | London, UK: The Institution of Engineering and Technology, 2020. |
| 형태사항 : | 1 online resource (xvii, 715 pages): illustrations. |
| 총서사항 : | IET materials, circuits and devices series; 64 |
| 서지주기 : | Includes bibliographical references and index (pages 697-715). |
| 내용주기 : | Evolution of monolithic phase-locked loops / Woogeun Rhee -- Fractional-N frequency synthesis / Sudharkar Pamarti -- Clock data recovery : a system perspective / Fulvio Spagna -- Silicon-based THz frequency synthesizers with wide locking range / Payam Heydari -- Time-to-digital converters / Fa Foster Dai and Hechen Wang -- Bang bang digital PLLs for wireless systems / Salvatore Levantino and Carolo Samori -- Hybrid PLLs / Mark Ferriss and Daniel Friedman -- Spur mitigation techniques for DPLL architecture / Cheng-Ru Ho and Mike Shuo-Wei Chen -- Fully synthesized digital PLL / Bangan Liu, Wei Deng, and Kenichi Okada -- Ultra-low power ADPLL / Hanli Liu and Kenichi Okada -- Integrated LC oscillators / Jun Li and Yiwu Tang -- Mm-wave and sub-THz CMOS VCOs / Xiaolong Liu and Howard C. Luong -- Ultra-low phase noise ADPLL for millimeter wave / Zhirui Zong and Robert Bogdan Staszewski -- DTC-based subsampling PLLs for low-noise synthesis and two-point modulation / Nereo Markulic, Jan Craninckx and Piet Wambacq -- Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering / Ni Xu -- An overview of CDR in ultra-high-speed wireline transceivers / Jay Im and Hongtao Zhang -- Clock and data recovery for optical links / Wei Zen Chen, Ming-Chiuan Su, and Yuan-Sheng Lee -- Digital clock and data recovery circuits / Saurabh Saxena and Pavan Kumar Hanumolu -- Spread spectrum clock generator : a low-cost EMI solution / Minyoung Song and Chulwoo Kim -- High-performance CMOS clock distribution / Xunjun Mo, Nijwm Wary and Tony Chan Carusone -- Sub-sampling PLL techniques / Xiang Gao, Eric Klumperink and Bram Nauta -- PLLs with nested frequency-locked loop / Taekwang Jang, Dong-in Kim and SeongHwan Cho -- Time amplified charge pump PLL / Ping-Ying Wang -- Multiplying DLLs / Shiheng Yang, Jun Yin, Pui-In Mak and Rui P. Martins -- Widespread PLLs / Long Kong and Behzad Razavi. |
| 요약 : | The book has 25 chapters and is divided into 5 parts. The first part which is about Basic architectures and system perspectives deals with Evolution of monolithic phase-locked loops; Fractional-N frequency synthesis; Clock data recovery: a system perspective; and Silicon-based THz frequency synthesizers with wide locking range. The second part which is about Digital-intensive phase-locked loops covers Time-to-digital converters; Bang-bang digital PLLs for wireless systems; Hybrid PLLs; Spur mitigation techniques for DPLL architecture; Fully synthesized digital PLL; and Ultra-low-power ADPLL. The third part which is about Low-noise frequency generation and modulation covers Integrated LC oscillators; Mm-wave and sub-THz CMOS VCOs; Ultra-low phase noise ADPLL for millimeter wave; DTC-based subsampling PLLs for low-noise synthesis and two-point modulation; and Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering. The fourth part which is about Clock-and-data recovery and clocking covers An overview of CDR in ultra-high-speed wireline transceivers; Clock and data recovery for optical links; Digital clock and data recovery circuits; Spread spectrum clock generator: a low-cost EMI solution; and High-performance CMOS clock distribution. Finally, part five which is about Advanced clock/frequency generation deals with Sub-sampling PLL techniques; PLLs with nested frequency-locked loop; Time amplified charge pump PLL; Multiplying DLLs; and Wideband PLLs. |
| 일반주제명 : | Phase-locked loops. -- |
| 일반주제명 : | Phase-locked loops -- |
| 일반주제명 : | charge pump circuits. -- |
| 일반주제명 : | clock and data recovery circuits. -- |
| 일반주제명 : | clock distribution networks. -- |
| 일반주제명 : | clocks. -- |
| 일반주제명 : | CMOS digital integrated circuits. -- |
| 일반주제명 : | digital phase locked loops. -- |
| 일반주제명 : | direct digital synthesis. -- |
| 일반주제명 : | electromagnetic interference. -- |
| 일반주제명 : | elemental semiconductors. -- |
| 일반주제명 : | field effect MIMIC. -- |
| 일반주제명 : | field effect MMIC. -- |
| 일반주제명 : | FIR filters. -- |
| 일반주제명 : | frequency locked loops. -- |
| 일반주제명 : | frequency modulation. -- |
| 일반주제명 : | LC circuits. -- |
| 일반주제명 : | low-power electronics. -- |
| 일반주제명 : | millimetre wave oscillators. -- |
| 일반주제명 : | MMIC oscillators. -- |
| 일반주제명 : | multiplying circuits. -- |
| 일반주제명 : | optical links. -- |
| 일반주제명 : | phase locked oscillators. -- |
| 일반주제명 : | phase noise. -- |
| 일반주제명 : | silicon. -- |
| 일반주제명 : | submillimetre wave integrated circuits. -- |
| 일반주제명 : | submillimetre wave oscillators. -- |
| 일반주제명 : | time-digital conversion. -- |
| 일반주제명 : | transceivers. -- |
| 일반주제명 : | voltage-controlled oscillators. -- |
| 개인저자 : | Rhee, Woogeun, 1968-, editor. |
| 기타형태 저록 : | Print version: Phase-locked frequency generation and clocking. [S.l.] : INST OF ENGIN AND TECH, 2020, 1785618857 |
| 언어 | 영어 |
| URL : |
|---|
예약
- 1. 예약현황은 홈페이지 로그인 후 예약 페이지에 확인 가능합니다.
- 2. 도착 통보된 예약자료 대출을 원하지 않는 경우에는 예약 현황에서 취소할 수 있습니다.
- 3. 기타 문의사항은 도서관에 문의 바랍니다.
무인예약대출
- 1. 무인예약대출 현황은 홈페이지 로그인 후 무인예약대출 페이지에 확인 가능합니다.
- 2. 무인예약대출자료 대출을 원하지 않는 경우에는 무인예약대출 페이지에서 신청 또는 접수상태인 경우만 취소할 수 있습니다.
- 3. 희망대출일은 신청일로부터 최대 1주일 까지 가능합니다.
- 4. 희망대출일을 선택하지 않은 경우 대출대기 통보 후 1주일까지 기기에서 대출가능합니다.
- 5. 기타 문의사항은 도서관에 문의 바랍니다.
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