MARC 닫기

• LDR

  01551cam a22003011u 45x0

• 001

  000000329298

• 005

  20120927134419

• 008

  920812s1993 us a b 001 eng

• 010

  ▼a  92029798

• 015

  ▼a  GB93-765

• 020

  ▼a  0792392817

• 040

  ▼a  DLC
  ▼c  DLC
  ▼d  UKM

• 049

  ▼a  KMAL
  ▼l  AZ0000160049

• 082

  ▼a  621.3819535
  ▼2  20

• 090

  ▼a  621.3819535
  ▼b  Sa6d

• 245

  ▼a  Design automation for timing-driven layout synthesis/
  ▼d  by Sachin S. Sapatnekar, Sung-Mo (Steve) Kang.

• 260

  ▼a  Boston:
  ▼b  Kluwer Academic Publishers,
  ▼c  c1993.

• 300

  ▼a  xx, 269 p.:
  ▼b  ill.;
  ▼c  25 cm.

• 440

  ▼a  The Kluwer international series in engineering and computer science;
  ▼v  SECS198.
  ▼a  VLSI, computer architecture, and digital signal processing

• 504

  ▼a  Includes bibliographical references (p. 247-266) and index.

• 650

  ▼a  Metal oxide semiconductors, Complementary
  ▼x  Design and construction
  ▼x  Data processing.

• 650

  ▼a  Integrated circuits
  ▼x  Very large scale integration
  ▼x  Design and construction
  ▼x  Data processing.

• 650

  ▼a  Computer-aided design.

• 653

  ▼a  DESIGN
  ▼a  AUTOMATION
  ▼a  FOR
  ▼a  TIMINGDRIVEN
  ▼a  LAYOUT
  ▼a  SYNTHESIS
  ▼a  THE
  ▼a  KLUWER
  ▼a  INTERNATIONAL
  ▼a  SERIES
  ▼a  IN
  ▼a  ENGINEERING
  ▼a  AND
  ▼a  COMPUTER
  ▼a  SCIENCE
  ▼a  VLSI
  ▼a  ARCHITECTURE
  ▼a  DIGITAL
  ▼a  SIGNAL
  ▼a  PROCESSING

• 700

  ▼a  Sapatnekar, Sachin S,

• 700

  ▼a  Kang, Sung-Mo,
  ▼d  1945-,

• 830

  ▼a  Kluwer international series in engineering and computer science;
  ▼v  SECS 198.

• 830

  ▼a  Kluwer international series in engineering and computer science.
  ▼p  VLSI, computer architecture, and digital signal processing.

• 991

  ▼a  단행본

• 090

  ▼a  621.3819535
  ▼b  Sa6d