MARC 닫기

• LDR

  01227nam 2200289 k 4500

• 001

  000000654303

• 005

  2051130121000

• 008

  010519s1984 us a 001a eng

• 020

  ▼a  0898381649

• 040

  ▼a  248023
  ▼c  248023

• 049

  ▼l  EM93255

• 082

  ▼a  621.38173
  ▼2  19

• 090

  ▼a  621.38173
  ▼b  L832l

• 100

  ▼a  Brayton, Robert King.

• 245

  ▼a  Logic minimization algorithms for VLSI synthesis/
  ▼d  by Robert K. Brayton ... [et al.].

• 260

  ▼a  Boston:
  ▼b  Kluwer Academic Publishers,
  ▼c  1984.

• 300

  ▼a  ix,193p.:
  ▼b  ill.;
  ▼c  25cm.

• 440

  ▼b  (The)Kluwer international series in engineering and computer science;
  ▼v  SECS 2.
  ▼a  VLSI, computer architecture, and digital signal processing

• 504

  ▼a  Includes bibliography: p.[174]-190 and index

• 653

  ▼a  LOGIC
  ▼a  MINIMIZATION
  ▼a  ALGORITHMS
  ▼a  VLSI
  ▼a  SYNTHESIS
  ▼a  COMPUTER
  ▼a  ARCHITECTURE
  ▼a  DIGITAL
  ▼a  SIGNAL
  ▼a  PROCESSING

• 740

  ▼a  Logic minimization algorithms for V.L.S.I. synthesis

• 950

  ▼b  \60000

• 965

  ▼a  Logic design

• 965

  ▼a  Integrated circuits
  ▼x  Very large scale integration

• 965

  ▼a  Integrated circuits
  ▼x  Design and construction
  ▼x  Data processing

• 965

  ▼a  Algorithms

• 965

  ▼a  Electronic equipment
  ▼x  Very large scale integrated circuits
  ▼x  Design

• 991

  ▼a  단행본

• 090

  ▼a  621.38173
  ▼b  L832l