MARC 닫기

• LDR

  01066oamoa2200277 u pc4

• 001

  000000307986

• 005

  20120927084614

• 008

  850116s1986 us a b 001 eng

• 010

  ▼a  85000078

• 020

  ▼a  0262111039

• 040

  ▼a  DLC
  ▼c  DLC
  ▼d  m/c

• 049

  ▼a  KMAL
  ▼l  AZ0000129002

• 082

  ▼a  621.38195
  ▼2  19

• 090

  ▼a  621.38195
  ▼b  K15r

• 100

  ▼a  Katevenis, Manolis G. H.

• 245

  ▼a  Reduced instruction set computer architectures for VLSI/
  ▼d  Manolis G.H. Katevenis.

• 260

  ▼a  Cambridge, Mass.:
  ▼b  MIT Press,
  ▼c  1986.

• 300

  ▼a  215 p.:
  ▼b  ill.;
  ▼c  23 cm.

• 440

  ▼a  ACM doctoral dissertation awards;
  ▼v  1984

• 500

  ▼a  Originally presented as author's thesis (Ph. D.)--University of California, Berkeley, 1983.

• 500

  ▼a  Includes index.

• 504

  ▼a  Bibliography: p. [201]-207.

• 650

  ▼a  Computer architecture.

• 650

  ▼a  Integrated circuits
  ▼x  Very large scale integration.

• 653

  ▼a  REDUCED
  ▼a  INSTRUCTION
  ▼a  SET
  ▼a  COMPUTER
  ▼a  ARCHITECTURES
  ▼a  FOR
  ▼a  VLSI
  ▼a  ACM
  ▼a  DOCTORAL
  ▼a  DISSERTATION
  ▼a  AWARDS
  ▼a  AWARD

• 830

  ▼a  ACM doctoral dissertation award;
  ▼v  1984.

• 991

  ▼a  단행본

• 090

  ▼a  621.38195
  ▼b  K15r