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• LDR

  01491oamoa2200313 u pc4

• 001

  000000310240

• 005

  20120927084624

• 008

  900924s1991 us a b 001 eng

• 010

  ▼a  90019256

• 015

  ▼a  GB91-29074

• 020

  ▼a  0792391322 (acid-free paper)

• 040

  ▼a  DLC
  ▼c  DLC
  ▼d  UKM

• 049

  ▼a  KMAL
  ▼l  AZ0000150722

• 082

  ▼a  621.3819535
  ▼2  20

• 090

  ▼a  621.3819535
  ▼b  L51h

• 245

  ▼a  Hardware annealing in analog VLSI neurocomputing/
  ▼d  by Bang W. Lee and Bing J. Sheu.

• 260

  ▼a  Boston:
  ▼b  Kluwer Academic Publishers,
  ▼c  1991.

• 300

  ▼a  xii, 234 p.:
  ▼b  ill.;
  ▼c  25 cm.

• 440

  ▼a  The Kluwer international series in engineering and computer science;
  ▼v  SECS 127.
  ▼a  VLSI, computer architecture, and digital signal processing

• 504

  ▼a  Includes bibliographical references (p. [219]-230) and index.

• 650

  ▼a  Neural networks (Computer science)

• 650

  ▼a  Neural computers
  ▼x  Circuits.

• 650

  ▼a  Integrated circuits
  ▼x  Very large scale integration.

• 650

  ▼a  Simulated annealing (Mathematics)

• 653

  ▼a  HARDWARE
  ▼a  ANNEALING
  ▼a  IN
  ▼a  ANALOG
  ▼a  VLSI
  ▼a  NEUROCOMPUTING
  ▼a  THE
  ▼a  KLUWER
  ▼a  INTERNATIONAL
  ▼a  SERIES
  ▼a  ENGINEERING
  ▼a  AND
  ▼a  COMPUTER
  ▼a  SCIENCE
  ▼a  ARCHITECTURE
  ▼a  DIGITAL
  ▼a  SIGNAL
  ▼a  PROCESSING

• 700

  ▼a  Lee, Bang W,

• 700

  ▼a  Sheu, Bing Jay,

• 830

  ▼a  Kluwer international series in engineering and computer science;
  ▼v  SECS 127.

• 830

  ▼a  Kluwer international series in engineering and computer science.
  ▼p  VLSI, computer architecture, and digital signal processing.

• 991

  ▼a  단행본

• 090

  ▼a  621.3819535
  ▼b  L51h