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• LDR

  01944nam a2200265 c 4500

• 001

  000000765087

• 005

  20101229120101

• 008

  091008s2010 nyua 000 0 eng

• 020

  ▼a  9780521872447 (hardback)

• 040

  ▼a  243002

• 100

  ▼a  Beerel, Peter A.

• 245

  ▼a  (A) Designer's guide to asynchronous VLSI /
  ▼d  [by] Peter A. Beerel ,
  ▼e  Recep O. Ozdag ,
  ▼e  Marcos Ferretti.

• 260

  ▼a  New York:
  ▼b  Cambridge University Press,
  ▼c  2010.

• 300

  ▼a  xii, 339 p.:
  ▼b  ill.;
  ▼c  26 cm.

• 505

  ▼a  Machine generated contents note: 1. Introduction; 2. Channel-based asynchronous design; 3. Modeling channel-based designs; 4. Pipeline performance; 5. Performance analysis and optimization; 6. Deadlock; 7. A taxonomy of design styles; 8. Synthesis-based controller design; 9. Micropipeline design; 10. Syntax-directed translation; 11. QDI pipeline templates; 12. Timed pipeline templates; 13. Single-track pipeline templates; 14. Asynchronous crossbar.

• 520

  ▼a  "Bypass the limitations of synchronous design and create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. The fundamentals of asynchronous design are covered, as is a large variety of design styles, while the emphasis throughout is on practical techniques and real-world applications"--Provided by publisher.

• 520

  ▼a  "This book provides an introduction to this diverse area of VLSI from a designer's point of view. Our goal is to enable designers to appreciate the many asynchronous design choices that may be readily available in the near future"--Provided by publisher.

• 650

  ▼a  Integrated circuits
  ▼x  Very large scale integration
  ▼x  Computer-aided design.

• 650

  ▼a  Integrated circuits
  ▼x  Very large scale integration
  ▼x  Design and construction.

• 700

  ▼a  Ozdag, Recep O,

• 700

  ▼a  Ferretti, Marcos,

• 950

  ▼b  ＄120.00

• 991

  ▼a  단행본

• 090

  ▼a  621.395
  ▼b  B415d