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00615nam ac200205 k 4500
000000174531
20220101120000
ta
051007s1999 us 000 eng
▼a 0139773983
▼a 123456
▼c 123456
▼d 211070
▼l WM7140
▼a TK7885.7
▼a TK7885.7
▼b C55
▼a Ciletti,Michael D
▼a Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL/
▼d Ciletti,Michael D.
▼a Upper Saddle River:
▼b Prentice Hall,
▼c 1999.
▼a xxii,727p.;
▼c 25cm+
▼e 2 CD-ROM.
▼a Verilog
▼a Computer hardware description language
▼b US$117
▼a 단행본
| 자료유형 : | 단행본 |
|---|---|
| ISBN : | 0139773983 |
| 분류기호 : | TK7885.7 |
| 개인저자 : | Ciletti,Michael D |
| 서명/저자사항 : | Modeling, Synthesis, and Rapid Prototyping with the Verilog HDL/ Ciletti,Michael D. |
| 발행사항 : | Upper Saddle River: Prentice Hall, 1999. |
| 형태사항 : | xxii,727p.; 25cm+ 2 CD-ROM. |
| 언어 | 영어 |
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